1. Field of the Invention
The present invention relates to a manufacturing method for an integrated semiconductor structure.
2. Description of the Related Art
Although in principle applicable to arbitrary integrated semiconductor structures, the following invention and the underlying problems will be explained with respect to integrated DRAM memory circuits in silicon technology.
The performance of integrated circuit metal oxide semiconductor transistors (MOSFETs) depends on a plurality of device parameters, such as gate dielectric thickness, transistor gate length and mobility of the charge carriers in the channel region. It is generally known that the application of stress in the transistor channel region is an important factor for increasing the carrier mobility. A number of methods have been utilized to apply stress to the transistor channel region including the formation of a high-stress liner over the transistor structure.
Silicon nitride stress liners are standard in logic process flows, but up to now not usable in DRAM process flows due to different array device processing steps. Currently, there is no applicable integration scheme which integrates a stress liner for peripheral transistors into a DRAM process flow such that an efficient process flow for manufacturing both array transistors and peripheral transistors can be achieved.
Moreover, it is generally known to provide gate stacks which are covered with insulating caps surrounding the electrical conductive gate conductors, which caps comprise a plurality of insulation layers. Hereinafter, the expression cap is used to define one or more insulation layer surrounding the electrical conductive gate conductors which may be present on top of and/or surrounding the electrical conductive gate conductors.